1. Field of the Invention
The present invention is related to a prognostic method; in particular, to a method for prognostic maintenance in semiconductor manufacturing equipments, which performs statistic analyses on significantly massive and complicated raw data outputted by semiconductor equipments, allowing in-situ engineers to predict the health level for prognostic repairs and maintenance on semiconductor equipments.
2. Description of Related Art
As semiconductor manufacturing technologies evolve, the surface area of integrated circuit has been largely reduced, which means small or minor defects generated during semiconductor processes may turn out to be critical factors for integrated circuit quality. Therein, the generation of defects may be caused by many potential problems, and one of these problems may be the health level of aging semiconductor equipments, which causes reduction in wafer yield. Therefore, four methods are commonly applied on current semiconductor equipments for repairs and maintenance so as to increase wafer yield:
1. Breakdown Maintenance (BDM)
This belongs to unplanned equipment repair; that is, engineers perform repairs and maintenance upon the occurrence of damage, breakdown, or failure in the semiconductor equipments.
2. Usage-Based Preventive Maintenance (UBM)
According to the times of usages in the semiconductor equipments, engineers perform repairs and maintenance thereon when a predetermined usage number is reached.
3. Time-Based Preventive Maintenance (TBM)
According to the duration of usages in the semiconductor equipments, engineers perform repairs and maintenance thereon when a predetermined duration of usage time is reached.
4. Condition-Based Maintenance (CBM)
It monitors the semiconductor equipments and collects monitor data, and then engineers determine whether it is required to perform repairs and maintenance based on the collected monitor data.
Nevertheless, the above-mentioned approaches of quantity-based maintenance as well as time-based maintenance can not prevent occurrence of failure in the semiconductor equipments beforehand, and even by means of the methods such as the said CBM, regarding the collected monitor data, there is currently still no effective methodology to predetermine the health condition of the semiconductor equipments at an early stage, so as to let engineers be able to perform repairs and maintenance on the semiconductor equipments before the problems therein generate undesirable impact on the wafer yield.
Presently, in the field of semiconductor, engineers use the Fault Detection and Classification (FDC) system to analyze the output data of the semiconductor equipments in order to be aware of the reasons causing wafer defects, so as to enabling appropriate adjustment on the semiconductor equipments by engineers, facilitating trouble shooting procedures and wafer yield enhancement. Initially, the FDC system is used to perform defect inspections, and presents the inspection result in a trend chart; then, engineers observe the variation in the generated trend chart for making decisions according to professional experiences in engineers themselves, so as to locate the causes of such defects (as the flowchart shown in FIG. 1); wherein the data provided by the semiconductor equipments is complicated and massive, thus the trend chart need to display a huge amount of information, and engineers have to spend much time on viewing the changes in the generated trend chart, thereby causing difficulties in problem analysis and tracking for engineers, and less able to control the health level of various semiconductor equipments, which accordingly leading to poor performance on semiconductor equipment management, thus unnecessarily wastes plenty of extra resources on problem finding yet with end results of incapability of wafer yield enhancement.
Presently, for example, a method is often used in the field of semiconductor for defect inspection parameter analysis (refer to FIG. 2), which can be used to analyze a plurality of lots of products. Each lot of products respectively has a lot number and is fabricated by means of a plurality of machineries; wherein one or more wafers in each lot of products pass through at least one defect inspection of product to generate a defect inspection parameter, and engineers determine where the problem is located in such a process chain which leads to undesirable wafer yield drop based on the information presented by these parameters. However, the solution provided by the above-said patent is excessively sophisticated, and engineers are required to set many rules to facilitate defect inspection analyses, as a result, it consumes too much time on rule building, leading to poor efficiency in resource application and less preferable practical usability.
As such, the inventors of the present invention have considered the aforementioned improvable defects and herein proposed the present invention with reasonable design and effectiveness in resolving the said drawbacks.